`include "../src/parameter.v"
module TOP#(
	parameter MEM_ROW_ADDR_WIDTH   = 15         ,
	parameter MEM_COL_ADDR_WIDTH   = 10         ,
	parameter MEM_BADDR_WIDTH      = 3          ,
	parameter MEM_DQ_WIDTH         =  32        ,
	parameter MEM_DQS_WIDTH        =  32/8
)(
	input                                sys_clk              ,//50Mhz
    input                                key8                  ,//key8
    input                                key7                  ,//key8
    input                                key6                  ,//key8
    input                                key5                  ,//key8
    input                                key4                  ,//key8
    input                                key3                  ,//key8
    input                                key2                  ,//key8
    input                                key1                  ,//key8    
    input                                rx                  ,//rx 
    output                                tx                  ,//tx           
//OV5647
    output  [1:0]                        cmos_init_done       ,//OV5640寄存器初始化完成
    //coms1	
    inout                                cmos1_scl            ,//cmos1 i2c 
    inout                                cmos1_sda            ,//cmos1 i2c 
    input                                cmos1_vsync          ,//cmos1 vsync
    input                                cmos1_href           ,//cmos1 hsync refrence,data valid
    input                                cmos1_pclk           ,//cmos1 pxiel clock
    input   [7:0]                        cmos1_data           ,//cmos1 data
    output                               cmos1_reset          ,//cmos1 reset
    //coms2
    inout                                cmos2_scl            ,//cmos2 i2c 
    inout                                cmos2_sda            ,//cmos2 i2c 
    input                                cmos2_vsync          ,//cmos2 vsync
    input                                cmos2_href           ,//cmos2 hsync refrence,data valid
    input                                cmos2_pclk           ,//cmos2 pxiel clock
    input   [7:0]                        cmos2_data           ,//cmos2 data
    output                               cmos2_reset          ,//cmos2 reset
//DDR
    output                               mem_rst_n                 ,
    output                               mem_ck                    ,
    output                               mem_ck_n                  ,
    output                               mem_cke                   ,
    output                               mem_cs_n                  ,
    output                               mem_ras_n                 ,
    output                               mem_cas_n                 ,
    output                               mem_we_n                  ,
    output                               mem_odt                   ,
    output      [MEM_ROW_ADDR_WIDTH-1:0] mem_a                     ,
    output      [MEM_BADDR_WIDTH-1:0]    mem_ba                    ,
    inout       [MEM_DQ_WIDTH/8-1:0]     mem_dqs                   ,
    inout       [MEM_DQ_WIDTH/8-1:0]     mem_dqs_n                 ,
    inout       [MEM_DQ_WIDTH-1:0]       mem_dq                    ,
    output      [MEM_DQ_WIDTH/8-1:0]     mem_dm                    ,
    output reg                           heart_beat_led            ,
    output                               ddr_init_done             ,//LED4
//MS72xx       
    output                               rstn_out                  ,/*synthesis PAP_MARK_DEBUG="1"*/ 
    output                               iic_tx_scl                ,
    inout                                iic_tx_sda                ,
    output iic_scl,
    inout iic_sda,
    output                               hdmi_int_led              ,//LED1,//HDMI_OUT初始化完成
//etherner
    input   rgmii_rxc,
    input   rgmii_rx_ctl,
    input   [3:0]  rgmii_rxd,
    output  rgmii_txc,
    output  rgmii_tx_ctl,
    output  [3:0]  rgmii_txd,    
    output phy_rstn,
    
//etherner2
    input   eth_rxc,
    input   eth_rx_ctl,
    input   [3:0]  eth_rxd,
    output  eth_txc,
    output  eth_tx_ctl,
    output  [3:0]  eth_txd,   
    output eth_rst_n, 

/*synthesis PAP_MARK_DEBUG="1"*/ 
/*synthesis PAP_MARK_DEBUG="1"*/ 
/*synthesis PAP_MARK_DEBUG="1"*/ 
/*synthesis PAP_MARK_DEBUG="1"*/

//HDMI_IN 
    input                                pixclk_in                ,                           
    input                                vs_in                     ,    
    input                                hs_in                     ,
    input                                de_in                     ,
    input      [7:0]                     r_in                      , 
    input      [7:0]                     g_in                      , 
    input      [7:0]                     b_in                      ,    
//HDMI_OUT
    output                               pix_clk                   ,//pixclk                           
    output     reg                          vs_out                    , 
    output     reg                          hs_out                    , 
    output     reg                          de_out                    ,
    output     reg [7:0]                     r_out                     , 
    output     reg [7:0]                     g_out                     , 
    output     reg [7:0]                     b_out         
);
/////////////////////////////////////////////////////////////////////////////////////
// ENABLE_DDR
parameter CTRL_ADDR_WIDTH = MEM_ROW_ADDR_WIDTH + MEM_BADDR_WIDTH + MEM_COL_ADDR_WIDTH;//28
parameter TH_1S = 27'd33000000;
/////////////////////////////////////////////////////////////////////////////////////
reg  [15:0]                 rstn_1ms            ;
wire                        cmos_scl            ;//cmos i2c clock
wire                        cmos_sda            ;//cmos i2c data
wire                        cmos_vsync          ;//cmos vsync
wire                        cmos_href           ;//cmos hsync refrence,data valid
wire                        cmos_pclk           ;//cmos pxiel clock
wire   [7:0]                cmos_data           ;//cmos data
wire                        cmos_reset          ;//cmos reset
wire                        initial_en          ;
wire[15:0]                  cmos1_d_16bit       ;
wire                        cmos1_href_16bit    ;
reg [7:0]                   cmos1_d_d0          ;
reg                         cmos1_href_d0       ;
reg                         cmos1_vsync_d0      ;
wire                        cmos1_pclk_16bit    ;
wire[15:0]                  cmos2_d_16bit       /*synthesis PAP_MARK_DEBUG="1"*/;
wire                        cmos2_href_16bit    /*synthesis PAP_MARK_DEBUG="1"*/;
reg [7:0]                   cmos2_d_d0          /*synthesis PAP_MARK_DEBUG="1"*/;
reg                         cmos2_href_d0       /*synthesis PAP_MARK_DEBUG="1"*/;
reg                         cmos2_vsync_d0      /*synthesis PAP_MARK_DEBUG="1"*/;
wire                        cmos2_pclk_16bit    /*synthesis PAP_MARK_DEBUG="1"*/;
wire[15:0]                  o_rgb565            ;
wire                        pclk_in_test_1        ;    
wire                        vs_in_test_1          ;
wire                        de_in_test_1          ;
wire[15:0]                  i_rgb565_1            ;
wire                        pclk_in_test_2        ;    
wire                        vs_in_test_2          ;
wire                        de_in_test_2          ;
wire[15:0]                  i_rgb565_2            ;
//axi bus   
wire [CTRL_ADDR_WIDTH-1:0]  axi_awaddr                 ;/*synthesis PAP_MARK_DEBUG="1"*/
wire                        axi_awuser_ap              ;
wire [3:0]                  axi_awuser_id              ;
wire [3:0]                  axi_awlen                  ;/*synthesis PAP_MARK_DEBUG="1"*/
wire                        axi_awready                ;/*synthesis PAP_MARK_DEBUG="1"*/
wire                        axi_awvalid                ;/*synthesis PAP_MARK_DEBUG="1"*/
wire [MEM_DQ_WIDTH*8-1:0]   axi_wdata                  ;/*synthesis PAP_MARK_DEBUG="1"*/
wire [MEM_DQ_WIDTH*8/8-1:0] axi_wstrb                  ;
wire                        axi_wready                 ;/*synthesis PAP_MARK_DEBUG="1"*/
wire [3:0]                  axi_wusero_id              ;
wire                        axi_wusero_last            ;
wire [CTRL_ADDR_WIDTH-1:0]  axi_araddr                 ;/*synthesis PAP_MARK_DEBUG="1"*/
wire                        axi_aruser_ap              ;
wire [3:0]                  axi_aruser_id              ;
wire [3:0]                  axi_arlen                  ;/*synthesis PAP_MARK_DEBUG="1"*/
wire                        axi_arready                ;/*synthesis PAP_MARK_DEBUG="1"*/
wire                        axi_arvalid                ;/*synthesis PAP_MARK_DEBUG="1"*/
wire [MEM_DQ_WIDTH*8-1:0]   axi_rdata                  ;/*synthesis PAP_MARK_DEBUG="1"*/
wire                        axi_rvalid                 ;/*synthesis PAP_MARK_DEBUG="1"*/
wire [3:0]                  axi_rid                    ;
wire                        axi_rlast                  ;/*synthesis PAP_MARK_DEBUG="1"*/
reg  [26:0]                 cnt                        ;
reg  [15:0]                 cnt_1                      ;
wire  [15:0]  rd_fifo_rd_data              ;
wire  [2:0]  frame_count;
wire core_clk;
/////////////////////////////////////////////////////////////////////////////////////

//PLL
wire clk_200m;
wire locked;
wire cfg_clk;
wire clk_25M;

pll u_pll (
    .clkin1   (  sys_clk    ),//50MHz
    .clkout0  (  pix_clk    ),//148.5M 1080P60
    .clkout1  (  cfg_clk    ),//10MHz
    .clkout2  (  clk_25M    ),//25M
    .clkout3  (clk_200m     ), // output
    .pll_lock (  locked     )
);

wire key8_flag;
key_filter #(
    .CNT_MAX ( 20'd999_999 ))
u_key_filter8 (
    .sys_clk                 ( sys_clk     ),
    .sys_rst_n               ( locked   ),
    .key_in                  ( key8      ),

    .key_flag                ( key8_flag    )//持续按下的时长
);

//配置7210
wire init_over_tx;
wire init_over_rx;
wire ms72xx_ctl_rstn;
ms72xx_ctl ms72xx_ctl(
    .clk             (  cfg_clk        ), //input       clk,
    .rst_n           (  rstn_out       ), //input       rstn,
    .init_over_tx    (  init_over_tx   ), //output      init_over,                                
    .init_over_rx    (  init_over_rx   ), //output      init_over,
    .iic_tx_scl      (  iic_tx_scl     ), //output      iic_scl,
    .iic_tx_sda      (  iic_tx_sda     ), //inout       iic_sda
    .iic_scl         (  iic_scl        ), //output      iic_scl,
    .iic_sda         (  iic_sda        )  //inout       iic_sda
);
assign    hdmi_int_led    =    init_over_tx; 

always @(posedge cfg_clk)
begin
    if(!locked)
        rstn_1ms <= 16'd0;
    else
    begin
        if(rstn_1ms == 16'h2710)
            rstn_1ms <= rstn_1ms;
        else
            rstn_1ms <= rstn_1ms + 1'b1;
    end
end
assign rstn_out = (rstn_1ms == 16'h2710);

/////////////////////////////////////////////////////////////////////////////////////

wire AXI_top_rstn,key_rstn;/*synthesis PAP_MARK_DEBUG="1"*/
assign key_rstn = rstn_out&&!key8_flag;
assign AXI_top_rstn = ddr_init_done&&key_rstn&&hdmi_int_led;

// // //////////////========================================================================
// greedy_snake_top Outputs
wire  hsync;/*synthesis PAP_MARK_DEBUG="1"*/
wire  vsync;/*synthesis PAP_MARK_DEBUG="1"*/
wire  vga_de;/*synthesis PAP_MARK_DEBUG="1"*/
wire  [23:0]  rgb;/*synthesis PAP_MARK_DEBUG="1"*/
greedy_snake_top  u_greedy_snake_top (
    .sys_clk                 ( sys_clk     ),
    .sys_rst_n               ( key_rstn   ),
    .key                     ( {key7,key6,key5,key4}         ),
    .touch_key               ( key3),

    .hsync                   ( hsync       ),
    .vsync                   ( vsync       ),
    .vga_de                  ( vga_de      ),
    .rgb                     ( rgb         )
);

// // //////////////========================================================================

always@(posedge pix_clk) begin
    r_out<=rgb[23:16];
    g_out<=rgb[15:8];
    b_out<=rgb[7:0];
    vs_out<=vsync;
    hs_out<=hsync; 
    de_out<=vga_de;
end

// // //////////////========================================================================

DDR3_50H u_DDR3_50H 
(
    .ref_clk                   (sys_clk            ),
    // .resetn                    (key_rstn           ),// input
    .resetn                    (rstn_out           ),// input
    .ddr_init_done             (ddr_init_done      ),// output
    .ddrphy_clkin              (core_clk           ),// output
    .pll_lock                  (pll_lock           ),// output

    .axi_awaddr                (axi_awaddr         ),// input [27:0]
    .axi_awuser_ap             (1'b0               ),// input
    .axi_awuser_id             (0      ),// input [3:0]
    .axi_awlen                 (axi_awlen          ),// input [3:0]
    .axi_awready               (axi_awready        ),// output
    .axi_awvalid               (axi_awvalid        ),// input
    .axi_wdata                 (axi_wdata          ),
    .axi_wstrb                 (32'hffffffff          ),// input [31:0]
    .axi_wready                (axi_wready         ),// output
    .axi_wusero_id             (                  ),// output [3:0]
    .axi_wusero_last           (axi_wusero_last    ),// output
    .axi_araddr                (axi_araddr         ),// input [27:0]
    .axi_aruser_ap             (1'b0               ),// input
    .axi_aruser_id             (0      ),// input [3:0]
    .axi_arlen                 (axi_arlen          ),// input [3:0]
    .axi_arready               (axi_arready        ),// output
    .axi_arvalid               (axi_arvalid        ),// input
    .axi_rdata                 (axi_rdata          ),// output [255:0]
    .axi_rid                   (            ),// output [3:0]
    .axi_rlast                 (axi_rlast          ),// output
    .axi_rvalid                (axi_rvalid         ),// output

    .apb_clk                   (1'b0               ),// input
    .apb_rst_n                 (1'b0               ),// input
    .apb_sel                   (1'b0               ),// input
    .apb_enable                (1'b0               ),// input
    .apb_addr                  (8'd0               ),// input [7:0]
    .apb_write                 (1'b0               ),// input
    .apb_ready                 (                   ), // output
    .apb_wdata                 (16'd0              ),// input [15:0]
    .apb_rdata                 (                   ),// output [15:0]
    .apb_int                   (                   ),// output

    .mem_rst_n                 (mem_rst_n          ),// output
    .mem_ck                    (mem_ck             ),// output
    .mem_ck_n                  (mem_ck_n           ),// output
    .mem_cke                   (mem_cke            ),// output
    .mem_cs_n                  (mem_cs_n           ),// output
    .mem_ras_n                 (mem_ras_n          ),// output
    .mem_cas_n                 (mem_cas_n          ),// output
    .mem_we_n                  (mem_we_n           ),// output
    .mem_odt                   (mem_odt            ),// output
    .mem_a                     (mem_a              ),// output [14:0]
    .mem_ba                    (mem_ba             ),// output [2:0]
    .mem_dqs                   (mem_dqs            ),// inout [3:0]
    .mem_dqs_n                 (mem_dqs_n          ),// inout [3:0]
    .mem_dq                    (mem_dq             ),// inout [31:0]
    .mem_dm                    (mem_dm             ),// output [3:0]
    //debug
    .debug_data                (                   ),// output [135:0]
    .debug_slice_state         (                   ),// output [51:0]
    .debug_calib_ctrl          (                   ),// output [21:0]
    .ck_dly_set_bin            (                   ),// output [7:0]
    .force_ck_dly_en           (1'b0               ),// input
    .force_ck_dly_set_bin      (8'h05              ),// input [7:0]
    .dll_step                  (                   ),// output [7:0]
    .dll_lock                  (                   ),// output
    .init_read_clk_ctrl        (2'b0               ),// input [1:0]
    .init_slip_step            (4'b0               ),// input [3:0]
    .force_read_clk_ctrl       (1'b0               ),// input
    .ddrphy_gate_update_en     (1'b0               ),// input
    .update_com_val_err_flag   (                   ),// output [3:0]
    .rd_fake_stop              (1'b0               ) // input
);

endmodule //TOP